A computational array of multipliers can be employed for various computer and electronics applications requiring parallel multiplication. For example, a computational array of multipliers can be used to obtain a sum of products from one or more input values. Typically, the multipliers in such a computational array are designed to multiply fixed point data. However, fixed point multipliers have a limited accuracy and a limited dynamic range of representable values, given practical restraints on data format size. These limitations on dynamic range and accuracy render fixed point multipliers insufficient for use in the performance of many computer functions.
Acceptable dynamic range and accuracy for these computer functions can often be obtained by using floating point data. Unfortunately, however, floating point multiplier circuits require a great deal of hardware overhead. This hardware overhead includes a greater physical area and a slower operation than fixed point multipliers. An entire computational array of floating point multipliers would require such a large physical area and would slow operation to such an extent that the performance of many computer functions would be prohibited. Thus, a more efficient computational array is needed for accomplishing parallel multiplications.